Courses / Module

• 1. Elucidate the critical issues in the design and testing of a digital logic silicon chip.
• 2. Interpret a functional design specification
• 3. Devise a design using Verilog.
• 4. Implement and validate the performance of a digital system using Verilog.
• 5. Work as a team in terms of project planning, review and implementation to deliver a working digital system using Verilog.

• Planning Learning activities consists of 9hrs of project work and 2 hrs of class tests.

• Module Graded (numeric value) or Ungraded (Pass/Not Passed): Graded

• Pass standard: 40%
• Could the result of this module be capped? No
• Pass 40% - students are not required to pass the assessment components separately – an overall pass mark of 40% is acceptable.
• Penalties: Laboratories, project and class tests cannot be repeated, in general.

• Are supplemental/resit registrations permitted? No
• This module is 100% continually assessed. Hence, there is no repeat Autumn examination, as there is no facility available for repeating the continuous assessment elements of the module. However, students who obtain between 30 – 40% are eligible for supplemental assessment over the summer period. In such instances, the final module grade will be capped at 40%.

• EE209 Digital Systems 2

• N/A

Reference Reading:

*Verilog HDL / S. Palnitkar, ISBN 0130449113

*Advanced digital design with Verilog HDL / Ciletti, Michael D.

*Introduction to VLSI circuits and systems / John P. Uyemura

For a full timetable search, go to NUIM Timetable. Venue locations can be found here.