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DIGITAL SYSTEMS 2

Module code: EE209FZ
Credits: 5
Semester: 1
Department: INTERNATIONAL ENGINEERING COLLEGE
International:

	Overview
	� Error control codes � Combinational logic with MSI and LSI � Sequential logic design - Flip-flops. � Programmable logic � Finite state machines (Mealy and Moore machines); Analysis. Design of minimal equivalent machines through state reduction. Analysis of invalid states. � Memory (ROM and RAM) and storage devices. SRAM and DRAM timing. � Analogue to Digital and Digital to Analogue converters. Nyquist rate converters. Non-ideal behaviour. � Multiplexers. Combinational logic design using Multiplexers as Universal Logic Modules � Introduction to FPGA technology - RTL level, comparison with Embedded processors/CPUs

Overview

� Error control codes
� Combinational logic with MSI and LSI
� Sequential logic design - Flip-flops.
� Programmable logic
� Finite state machines (Mealy and Moore machines); Analysis. Design of minimal equivalent machines through state reduction. Analysis of invalid states.
� Memory (ROM and RAM) and storage devices. SRAM and DRAM timing.
� Analogue to Digital and Digital to Analogue converters. Nyquist rate converters. Non-ideal behaviour.
� Multiplexers. Combinational logic design using Multiplexers as Universal Logic Modules
� Introduction to FPGA technology - RTL level, comparison with Embedded processors/CPUs

	Learning Outcomes
	On successful completion of the module, students should be able to: Perform calculations using different number systems. Distinguish between different error control codes. Design combinational logic circuits using multiplexers as universal logic modules. Analyse and design Finite State Machines. Outline the key features of memory and storage devices (RAM, ROM etc.). Explain the basic operation of Analogue to Digital and Digital to Analogue converters. Outline the difference between CPUs and FPGAs. Explain the function of both CPUs and FPG

Learning Outcomes

Teaching & Learning methods

Assessment

	Autumn Supplementals/Resits
	Are supplemental/resit registrations permitted? Yes The continuous assessment mark is carried forward as there is no facility for repeating the continuous assessment elements of the course. University scheduled written examination (Autumn): 120 minutes

	Additional Reading
	Floyd, Thomas L., Digital fundamentals, (7th ed.), Prentice Hall, 1999. Mano, M. Morris, Digital design, (2nd ed.), Prentice-Hall, 1991. Wakerly, John F., Digital design : principles and practices, (3rd ed.), Prentice Hall, 2001.

	Timetable
	This timetable is not currently available, please contact the International Engineering College Department.

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Courses / Module

DIGITAL SYSTEMS 2